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july 2002 1/25 ? VIPER20/sp/dip - VIPER20a/asp/adip smps primary i.c. 1 n adjustable switching frequency up to 200 khz n current mode control n soft start and shut down control n automatic burst mode operation in stand-by condition able to meet blue angel norm (<1w total power consumption) n internally trimmed zener reference n undervoltage lock-out with hysteresis n integrated start-up supply n avalanche rugged n overtemperature protection n low stand-by current n adjustable current limitation description VIPER20/20a, made using vipower m0 technology, combines on the same silicon chip a state-of-the-art pwm circuit together with an optimized high voltage avalanche rugged vertical power mosfet (620v or 700v / 0.5a). typical applications cover off line power supplies with a secondary power capability of 10w in wide range condition and 20w in single range or with doubler configuration. it is compatible from both primary or secondary regulation loop despite using around 50% less components when compared with a discrete solution. burst mode operation is an additional feature of this device, offering the possibility to operate in stand-by mode without extra components. type v dss i n r ds(on) VIPER20/sp/dip 620v 0.5 a 16 w VIPER20a/asp/adip 700v 0.5 a 18 w block diagram pentawatt hv pentawatt hv (022y) 1 10 powerso-10 ? vdd osc comp drain source 13 v uvlo logic security latch pwm latch ff ff r/s s q s r1 r2 r3 q oscillator overtemp. detector error amplifier _ + 0.5 v + _ 1.7 m s delay 250 ns blanking current amplifier on/off 0.5v 6 v/a _ + + _ 4.5 v fc00491 dip-8
2/25 VIPER20/sp/dip - VIPER20a/asp/adip absolute maximum rating thermal data (*) when mounted using the minimum recommended pad size on fr-4 board. (#) on multylayer pcb. connection diagrams (top view) current and voltage conventions symbol parameter value unit v ds continuous drain-source voltage (t j =25 to 125c) for VIPER20/sp/dip for VIPER20a/asp/adip -0.3 to 620 -0.3 to 700 v v i d maximum current internally limited a v dd supply voltage 0 to 15 v v osc voltage range input 0 to v dd v v comp voltage range input 0 to 5 v i comp maximum continuous current 2ma v esd electrostatic discharge (r =1.5k w ; c=100pf) 4000 v i d(ar) avalanche drain-source current, repetitive or not repetitive (t c =100c; pulse width limited by t j max; d < 1%) for VIPER20/sp/dip for VIPER20a/asp/adip 0.5 0.4 a a p tot power dissipation at t c =25o c57w t j junction operating temperature internally limited c t stg storage temperature -65 to 150 c symbol parameter pentawatt powerso-10 ? (*) dip-8 unit r thj-pin thermal resistance junction-pin max 20 c/w r thj-case thermal resistance junction-case max 2.0 2.0 c/w r thj-amb. thermal resistance ambient-case max 70 60 35 (#) c/w 1 pentawatt hv pentawatt hv (022y) powerso-10 ? - + 13v osc comp source drain vdd v comp v osc v dd v ds i comp i osc i dd i d fc00020 1 4 8 5 osc vdd source comp drain drain drain drain sc10540 dip-8
VIPER20/sp/dip - VIPER20a/asp/adip 3/25 ordering numbers pins functional description drain pin: integrated power mosfet drain pin. it provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. the device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, pcb stray inductance, and allowing a snubberless operation for low output power. source pin: power mosfet source pin. primary side circuit common ground connection. vdd pin: this pin provides two functions: - it corresponds to the low voltage supply of the control part of the circuit. if v dd goes below 8v, the start-up current source is activated and the output power mosfet is switched off until the v dd voltage reaches 11v. during this phase, the internal current consumption is reduced, the v dd pin sources a current of about 2ma and the comp pin is shorted to ground. after that, the current source is shut down, and the device tries to start up by switching again. - this pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. in case of primary regulation, an internal 13v trimmed reference voltage is used to maintain v dd at 13v. for secondary regulation, a voltage between 8.5v and 12.5v will be put on v dd pin by transformer design, in order to stick the output of the transconductance amplifier to the high state. the comp pin behaves as a constant current source, and can easily be connected to the output of an optocoupler. note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the v dd voltage, which cannot overpass 13v. the output voltage will be somewhat higher than the nominal one, but still under control. comp pin: this pin provides two functions: - it is the output of the error transconductance amplifier, and allows for the connection of a compensation network to provide the desired transfer function of the regulation loop. its bandwidth can easily be adjusted to the needed value with usual components value. as stated above, secondary regulation configurations are also implemented through the comp pin. - when the comp voltage goes below 0.5v, the shut-down of the circuit occurs, with a zero duty cycle for the power mosfet. this feature can be used to switch off the converter, and is automatically activated by the regulation loop (whatever is the configuration) to provide a burst mode operation in case of negligible output power or open load condition. osc pin: an r t -c t network must be connected on that pin to define the switching frequency. note that despite the connection of r t to v dd , no significant frequency change occurs for v dd varying from 8v to 15v. it also provides a synchronization capability, when connected to an external frequency source. pentawatt hv pentawatt hv (022y) powerso-10 ? dip-8 VIPER20 VIPER20 (022y) VIPER20sp VIPER20dip VIPER20a VIPER20a (022y) VIPER20asp VIPER20adip 1
4/25 VIPER20/sp/dip - VIPER20a/asp/adip avalanche characteristics electrical characteristics (t j =25c; v dd =13v, unless otherwise specified) power section (1) on inductive load, clamped. supply section symbol parameter max value unit i d(ar) avalanche current, repetitive or not repetitive (pulse widht limited by t j max; d < 1%) for VIPER20/sp/dip for VIPER20a/asp/adip (see fig.12) 0.5 0.4 a a e (ar) single pulse avalanche energy (starting t j =25oc, i d =i d(ar) ) (see fig.12) 10 mj symbol parameter test conditions min typ max unit bv dss drain-source voltage i d =1ma; v comp =0v for VIPER20/sp/dip for VIPER20a/asp/adip (see fig.5) 620 700 v v i dss off-state drain current v comp =0v; t j =125c v ds =620v for VIPER20/sp/dip v ds =700v for VIPER20a/asp/adip 1.0 1.0 ma ma r ds(on) static drain-source on resistance i d =0.4a for VIPER20/sp/dip for VIPER20a/asp/adip i d =0.4a; t j =100c for VIPER20/sp/dip for VIPER20a/asp/adip 13.5 15.5 16 18 29 32 w w w w t f fall time i d =0.2a; v in =300v (1) (see fig. 3) 100 ns t r rise time i d =.4a; v in =300v (1) (see fig. 3) 50 ns c oss output capacitance v ds =25v 90 pf symbol parameter test conditions min typ max unit i ddch start-up charging current v dd =5v; v ds =35v (see fig. 2 and fig. 15) -2 ma i dd0 operating supply current v dd =12v; f sw =0khz (see fig. 2) 12 16 ma i dd1 operating supply current v dd =12v; f sw =100khz 13 ma i dd2 operating supply current v dd =12v; f sw =200khz 14 ma v ddoff undervoltage shutdown (see fig. 2) 7.5 8 9 v v ddon undervoltage reset (see fig. 2) 11 12 v v ddhyst hysteresis start-up (see fig. 2) 2.4 3 v
VIPER20/sp/dip - VIPER20a/asp/adip 5/25 electrical characteristics (continued) oscillator section error amplifier section pwm comparator section shutdown and overtemperature section symbol parameter test conditions min typ max unit f sw oscillator frequency total variation r t =8.2k w ; c t =2.4nf v dd =9 to 15v; with r t 1%; c t 5% (see fig. 6 and fig. 9) 90 100 110 khz v oscih oscillator peak voltage 7.1 v v oscil oscillator valley voltage 3.7 v symbol parameter test conditions min typ max unit v ddreg v dd regulation point i comp =0ma (see fig. 1) 12.6 13 13.4 v d v ddreg total variation t j =0 to 100c 2 % g bw unity gain bandwidth from input =v dd to output = v comp comp pin is open (see fig. 10) 150 khz a vol open loop voltage gain comp pin is open (see fig. 10) 45 52 db g m dc transconductance v comp =2.5v (see fig. 1) 1.1 1.5 1.9 ma/v v complo output low level i comp = -400a; v dd =14v 0.2 v v comphi output high level i comp =400a; v dd =12v 4.5 v i complo output low current capability v comp =2.5v; v dd =14v -600 a i comphi output high current capability v comp =2.5v; v dd =12v 600 a symbol parameter test conditions min typ max unit h id d v comp / d i dpeak v comp =1 to 3 v 4.267.8v/a v compoff v comp offset i dpeak =10ma 0.5 v i dpeak peak current limitation v dd =12v; comp pin open 0.5 0.67 0.9 a t d current sense delay to turn-off i d =1a 250 ns t b blanking time 250 360 ns t on(min) minimum on time 350 ns symbol parameter test conditions min typ max unit v compth restart threshold (see fig. 4) 0.5 v t dissu disable set up time (see fig. 4) 1.7 5 s t tsd thermal shutdown temperature (see fig. 8) 140 170 190 c t hyst thermal shutdown hysteresis (see fig. 8) 40 c
6/25 VIPER20/sp/dip - VIPER20a/asp/adip figure 3: transition time figure 4: shut down action figure 5: breakdown voltage vs. temperature figure 6: typical frequency variation figure 1: v dd regulation point figure 2: undervoltage lockout i comp i comphi i complo v ddreg 0 v dd slope = gm in ma/v fc00150 v ddon i ddch i dd0 v dd v ddoff v ds = 35 v fsw = 0 i dd v ddhyst fc00170 i d v ds t t tf tr 10% ipeak 10% v d 90% v d fc00160 vcomp vosc id t tdissu t t enable disable enable vcompth fc00060 temperature (c) fc00180 0 20406080100120 0.95 1 1.05 1.1 1.15 bv dss (normalized) temperature (c) 0 20406080100120140 -5 -4 -3 -2 -1 0 1 fc00190 (%)
VIPER20/sp/dip - VIPER20a/asp/adip 7/25 figure 7: start-up waveforms figure 8: overtemperature protection sc10191 t j t tsd -t hyst t tsc v dd v ddon v ddoff i d v comp t t t t
8/25 VIPER20/sp/dip - VIPER20a/asp/adip figure 9: oscillator 1 rt ct osc vdd ~360 w clk fc00050 1 2 3 5 10 20 30 50 30 50 100 200 300 500 1,000 rt (k w ) frequency (khz) oscillator frequency vs rt and ct ct = 1.5 nf ct = 2.7 nf ct = 4.7 nf ct = 10 nf fc00030 fc00030 for r t >1.2k w and c t 3 15nf if f sw 40khz f sw 2.3 r t c t ----------- - 1 550 r t 150 C --------------------- - C ? ?? = c t fsw 40khz 15nf 22nf forbidden area forbidden area ct(nf) = fsw(khz) 880
VIPER20/sp/dip - VIPER20a/asp/adip 9/25 figure 10: error amplifier frequency response figure 11: error amplifier phase response 1 0.001 0.01 0.1 1 10 100 1,000 (20) 0 20 40 60 frequency (khz) voltage gain (db) rcomp = + rcomp = 270k rcomp = 82k rcomp = 27k rcomp = 12k fc00200 0.001 0.01 0.1 1 10 100 1,000 (50) 0 50 100 150 200 frequency (khz) phase () rcomp = + rcomp = 270k rcomp = 82k rcomp = 27k rcomp = 12k fc00210
10/25 VIPER20/sp/dip - VIPER20a/asp/adip figure 12: avalanche test circuit 1 fc00196 u1 VIPER20 13v osc comp source drain vdd - + 23 54 1 r3 100 r2 1k bt2 12v c1 47uf 16v q1 2 x sthv102fi in parallel r1 47 l1 1mh generator input 500us pulse bt1 0 to 20v
11/25 VIPER20/sp/dip - VIPER20a/asp/adip 1 figure 13: off line power supply with auxiliary supply feedback figure 14: off line power supply with optocoupler feedback ac in +vcc gnd f1 br1 d3 r9 c1 r7 c4 c2 tr2 r1 c3 d1 d2 c10 tr1 c9 c7 l2 r3 c6 c5 r2 VIPER20 - + 13v osc comp source drain vdd fc00401 c11 ac in f1 br1 d3 r9 c1 r7 c4 c2 tr2 r1 c3 d1 d2 c10 tr1 c9 c7 l2 +vcc gnd c8 c5 r2 VIPER20 u2 r4 r5 iso1 r6 r3 c6 - + 13v osc comp source drain vdd fc00411 c11
12/25 VIPER20/sp/dip - VIPER20a/asp/adip operation description: current mode topology the current mode control method, like the one integrated in the VIPER20/20a uses two control loops - an inner current control loop and an outer loop for voltage control. when the power mosfet output transistor is on, the inductor current (primary side of the transformer) is monitored with a sensefet technique and converted into a voltage v s proportional to this current. when v s reaches v comp (the amplified output voltage error) the power switch is switched off. thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer. excellent d.c. open loop and dynamic line regulation is ensured due to the inherent input voltage feedforward characteristic of the current mode control. this results in an improved line regulation, instantaneous correction to line changes and better stability for the voltage regulation loop. current mode topology also ensures good limitation in the case of short circuit. during the first phase the output current increases slowly following the dynamic of the regulation loop. then it reaches the maximum limitation current internally set and finally stops because the power supply on v dd is no longer correct. for specific applications the maximum peak current internally set can be overridden by limiting the voltage excursion externally on the comp pin. an integrated blanking filter inhibits the pwm comparator output for a short time after the integrated power mosfet is switched on. this function prevents anomalous or premature termination of the switching pulse in the case of current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time. stand-by mode stand-by operation in nearly open load condition automatically leads to a burst mode operation allowing voltage regulation on the secondary side. the transition from normal operation to burst mode operation happens for a power p stby given by: where: l p is the primary inductance of the transformer. f sw is the normal switching frequency. i stby is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. this current can be computed as: t b + t d is the sum of the blanking time and of the propagation time of the internal current sense and comparator, and roughly represents the minimum on time of the device. note that p stby may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. as soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the 13v regulation level forcing the output voltage of the transconductance amplifier to low state (v comp < v compth ). this situation leads to the shutdown mode where the power switch is maintained in the off state, resulting in missing cycles and zero duty cycle. as soon as v dd gets back to the regulation level and the v compth threshold is reached, the device operates again. the above cycle repeats itself indefinitely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. the equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input mains lines. this mode of operation allows the VIPER20/20a to meet the new german "blue angel" norm with less than 1w total power consumption for the system when working in stand-by. the output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. the amplitude of this ripple is low, because of the output capacitors and because of the low output current drawn in such conditions. the normal operation resumes automatically when the power gets back levels which are higher than p stby . high voltage start-up current source an integrated high voltage current source provides a bias current from the drain pin during the start- up phase. this current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and are also provided to the external capacitor connected to the v dd pin. as soon as the voltage on this pin reaches the high voltage threshold v ddon of the p stby 1 2 -- - l p i 2 stby f sw = i stby t b t d + () v in l p -------------------------------- =
13/25 VIPER20/sp/dip - VIPER20a/asp/adip uvlo logic, the device turns into active mode and starts switching. the start up current generator is switched off, and the converter should normally provide the needed current on the v dd pin through the auxiliary winding of the transformer, as shown on figure 15. in case of abnormal condition where the auxiliary winding is unable to provide the low voltage supply current to the v dd pin (i.e. short circuit on the output of the converter), the external capacitor discharges itself down to the low threshold voltage v ddoff of the uvlo logic, and the device gets back to the inactive state where the internal circuits are in standby mode and the start up current source is activated. the converter enters an endless start up cycle, with a start-up duty cycle defined by the ratio of charging current towards discharging when the VIPER20/20a tries to start. this ratio is fixed by design from 2 to 15, which gives a 12% start up duty cycle while the power dissipation at start up is approximately 0.6 w, for a 230 vrms input voltage. this low value of start-up duty cycle prevents the stress of the output rectifiers and of the transformer when in short circuit. the external capacitor c vdd on the v dd pin must be sized according to the time needed by the converter to start up, when the device starts switching. this time t ss depends on many parameters, among which transformer design, output capacitors, soft start feature and compensation network implemented on the comp pin. the following formula can be used for defining the minimum capacitor needed: where: i dd is the consumption current on the v dd pin when switching. refer to specified i dd1 and i dd2 values. t ss is the start up time of the converter when the device begins to switch. worst case is generally at full load. v ddhyst is the voltage hysteresis of the uvlo logic. refer to the minimum specified value. soft start feature can be implemented on the comp pin through a simple capacitor which will also be used as the compensation network. in this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. in case of a large regulation loop bandwidth is mandatory, the schematics in figure 16 can be used. it mixes a high performance compensation network together with a separate high value soft start capacitor. both soft start time and regulation loop bandwidth can be adjusted separately. if the device is intentionally shut down by putting the comp pin to ground, the device is also performing start-up cycles, and the v dd voltage is oscillating between v ddon and v ddoff . this voltage can be used for supplying external functions, provided that their consumption doesn't exceed 0.5ma. figure 17 shows a typical application of this function, with a latched shut down. once the "shutdown" signal has been activated, the device remains in the off state until the input voltage is removed. c vdd i dd t ss v ddhyst ------------------------- - > figure 15: behavior of the high voltage current source at start-up ref. undervoltage lock out logic 15 ma 1 ma 3 ma 2 ma 15 ma vdd drain source VIPER20 auxiliary primary winding vdd t vddoff vddon start up duty cycle ~ 12% c vdd fc00101a
14/25 VIPER20/sp/dip - VIPER20a/asp/adip transconductance error amplifier the VIPER20/20a includes a transconductance error amplifier. transconductance gm is the change in output current (i comp ) versus change in input voltage (v dd ). thus: the output impedance z comp at the output of this amplifier (comp pin) can be defined as: this last equation shows that the open loop gain a vol can be related to g m and z comp : a vol = g m x z comp where g m value for viper50/50a is 1.5 ma/v typically. g m is well defined by specification, but z comp and therefore a vol are subject to large tolerances. an impedance z can be connected between the comp pin and ground in order to define more accurately the transfer function f of the error amplifier, according to the following equation, very similar to the one above: f (s) = gm x z(s) the error amplifier frequency response is reported in figure 10 for different values of a simple resistance connected on the comp pin. the unloaded transconductance error amplifier shows an internal z comp of about 330 k w . more complex impedance can be connected on the comp pin to achieve different compensation laws. a capacitor will provide an integrator function, thus eliminating the dc static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin. this configuration is illustrated in figure 18. as shown in figure 18 an additional noise filtering capacitor of 2.2 nf is generally needed to avoid any high frequency interference. it can also be interesting to implement a slope compensation when working in continuous mode with duty cycle higher than 50%. figure 19 shows such a configuration. note that r1 and c2 build the classical compensation network, and q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. external clock synchronization the osc pin provides a synchronisation capability, when connected to an external frequency source. figure 20 shows one possible schematic to be adapted depending on the specific needs. if the proposed schematic is used, the pulse duration must be kept at a low value (500ns is sufficient) for minimizing consumption. the optocoupler must be able to provide 20ma through the optotransistor. primary peak current limitation the primary i dpeak current and, as resulting effect, the output power can be limited using the simple circuit shown in figure 21. the circuit based on q1, r 1 and r 2 clamps the voltage on the g m ? i comp ? v dd ------------------------ = z comp ? v comp ? i comp -------------------------- - 1 m g --------- ? v comp ? v dd -------------------------- - == figure 16: mixed soft start and compensation figure 17: latched shut down - + 13v osc comp source drain vdd VIPER20 r1 c1 + c2 d1 r2 r3 d2 d3 + c3 auxiliary winding fc00431 c4 - + 13v osc comp source drain vdd VIPER20 shutdown q1 q2 r1 r2 r3 r4 d1 fc00440
15/25 VIPER20/sp/dip - VIPER20a/asp/adip comp pin in order to limit the primary peak current of the device to a value: where: the suggested value for r 1 +r 2 is in the range of 220k w . over-temperature protection: over-temperature protection is based on chip temperature sensing. the minimum junction temperature at which over-temperature cut-out occurs is 140 o c while the typical value is 170 o c. the device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40 o c below the shutdown value (see figure 8). i dpeak v comp 0.5 C h id ------------------------------------- = v comp 0.6 r 1 r 2 + r 2 --------------------- - = figure 18: typical compensation network figure 20: external clock synchronization figure 19: slope compensation figure 21: current limitation circuit example - + 13v osc comp source drain vdd VIPER20 r1 c1 fc00451 c2 - + 13v osc comp source drain vdd VIPER20 r1 r2 q1 c2 c1 r3 fc00461 c3 - + 13v osc comp source drain vdd VIPER20 10 k w fc00470 - + 13v osc comp source drain vdd VIPER20 r1 r2 q1 fc00480
16/25 VIPER20/sp/dip - VIPER20a/asp/adip figure 22: input voltage surges protection electrical over stress ruggedness the viper may be submitted to electrical over stress caused by violent input voltage surges or lightning. following the enclosed layout considerations chapter rules is the most of the time sufficient to prevent catastrophic damages, however in some cases the voltage surges coupled through the transformer auxiliary winding can overpass the v dd pin absolute maximum rating voltage value. such events may trigger the v dd internal protection circuitry which could be damaged by the strong discharge current of the v dd bulk capacitor. the simple rc filter shown in figure 22 can be implemented to improve the application immunity to such surges. c1 bulk capacitor d1 r1 (optional) c2 22nf auxilliary winding 13v osc comp source drain vdd - + viperxx0 r2 39r
17/25 VIPER20/sp/dip - VIPER20a/asp/adip 1 figure 23: recommended layout layout considerations some simple rules insure a correct running of switching power supplies. they may be classified into two categories: - to minimize power loops: the way the switched power current must be carefully analyzed and the corresponding paths must present the smallest possible inner loop area. this avoids radiated emc noises, conducted emc noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side. - to use different tracks for low level signals and power ones. the interferences due to a mixing of signal and power may result in instabilities and/or anomalous behavior of the device in case of violent power surge (input overvoltages, output short circuits...). in case of viper, these rules apply as shown in figure 23. the loops c1-t1-u1, c5-d2-t1, c7-d1- t1 must be minimized. c6 must be as close as possible to t1. the signal components c2, iso1, c3 and c4 use a dedicated track to be connected directly to the source of the device. t1 u1 viperxx0 13v osc comp source drain vdd - + 1 5 2 3 4 c4 c2 c5 c1 d2 r1 r2 d1 c7 c6 c3 iso1 )urplqsxw glrghveulgjh 7rvhfrqgdu\ ilowhulqjdqgordg fc00500
18/25 VIPER20/sp/dip - VIPER20a/asp/adip dim. mm. inch min. typ max. min. typ. max. a 3.35 3.65 0.132 0.144 a (*) 3.4 3.6 0.134 0.142 a1 0.00 0.10 0.000 0.004 b 0.40 0.60 0.016 0.024 b (*) 0.37 0.53 0.014 0.021 c 0.35 0.55 0.013 0.022 c (*) 0.23 0.32 0.009 0.0126 d 9.40 9.60 0.370 0.378 d1 7.40 7.60 0.291 0.300 e 9.30 9.50 0.366 0.374 e2 7.20 7.60 0.283 300 e2 (*) 7.30 7.50 0.287 0.295 e4 5.90 6.10 0.232 0.240 e4 (*) 5.90 6.30 0.232 0.248 e 1.27 0.050 f 1.25 1.35 0.049 0.053 f (*) 1.20 1.40 0.047 0.055 h 13.80 14.40 0.543 0.567 h (*) 13.85 14.35 0.545 0.565 h 0.50 0.002 l 1.20 1.80 0.047 0.070 l (*) 0.80 1.10 0.031 0.043 a 0o 8o 0o 8o a (*) 2o 8o 2o 8o powerso-10 ? mechanical data (*) muar only poa p013p detail "a" plane seating a l a1 f a1 h a d d1 = = = = e4 0.10 a c a b b detail "a" seating plane e2 10 1 eb he 0.25 p095a
19/25 VIPER20/sp/dip - VIPER20a/asp/adip 1 1 dim. mm. inch min. typ max. min. typ. max. a 4.30 4.80 0.169 0.189 c 1.17 1.37 0.046 0.054 d 2.40 2.80 0.094 0.11 e 0.35 0.55 0.014 0.022 f 0.60 0.80 0.024 0.031 g1 4.91 5.21 0.193 0.205 g2 7.49 7.80 0.295 0.307 h1 9.30 9.70 0.366 0.382 h2 10.40 0.409 h3 10.05 10.40 0.396 0.409 l 15.60 17.30 6.14 0.681 l1 14.60 15.22 0.575 0.599 l2 21.20 21.85 0.835 0.860 l3 22.20 22.82 0.874 0.898 l5 2.60 3 0.102 0.118 l6 15.10 15.80 0.594 0.622 l7 6 6.60 0.236 0.260 m 2.50 3.10 0.098 0.122 m1 4.50 5.60 0.177 0.220 r 0.50 0.02 v4 90 (typ) diam 3.65 3.85 0.144 0.152 p023h3 pentawatt hv mechanical data
20/25 VIPER20/sp/dip - VIPER20a/asp/adip 1 a c h2 h3 h1 l5 dia l3 l6 l7 f g1 g2 l l1 d r m m1 e resin between leads v4 dim. mm. inch min. typ max. min. typ. max. a 4.30 4.80 0.169 0.189 c 1.17 1.37 0.046 0.054 d 2.40 2.80 0.094 0.110 e 0.35 0.55 0.014 0.022 f 0.60 0.80 0.024 0.031 g1 4.91 5.21 0.193 0.205 g2 7.49 7.80 0.295 0.307 h1 9.30 9.70 0.366 0.382 h2 10.40 0.409 h3 10.05 10.40 0.396 0.409 l 16.42 17.42 0.646 0.686 l1 14.60 15.22 0.575 0.599 l3 20.52 21.52 0.808 0.847 l5 2.60 3.00 0.102 0.118 l6 15.10 15.80 0.594 0.622 l7 6.00 6.60 0.236 0.260 m 2.50 3.10 0.098 0.122 m1 5.00 5.70 0.197 0.224 r 0.50 0.020 v4 90 90 diam. 3.70 3.90 0.146 0.154 pentawatt hv 022y (vertical high pitch) mechanical data
21/25 VIPER20/sp/dip - VIPER20a/asp/adip dim. mm. min. typ max. a 5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.26 e1 6.10 6.35 7.11 e2.54 ea 7.62 eb 10.92 l 2.92 3.30 3.81 package weight gr. 470 p001 plastic dip-8 mechanical data
22/25 VIPER20/sp/dip - VIPER20a/asp/adip 1 powerso-10 ? suggested pad layout 1 tape and reel shipment (suffix 13tr) reel dimensions all dimensions are in mm. base q.ty 600 bulk q.ty 600 a (max) 330 b (min) 1.5 c ( 0.2) 13 f 20.2 g (+ 2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 ( 0.1) 4 component spacing p 24 hole diameter d ( 0.1/-0) 1.5 hole diameter d1 (min) 1.5 hole position f ( 0.05) 11.5 compartment depth k (max) 6.5 hole spacing p1 ( 0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets saled with cover tape. user direction of feed 6.30 10.8 - 11 14.6 - 14.9 9.5 1 2 3 4 5 1.27 0.67 - 0.73 0. 54 - 0.6 10 9 8 7 6 b a c all dimensions are in mm. base q.ty bulk q.ty tube length ( 0.5) a b c ( 0.1) casablanca 50 1000 532 10.4 16.4 0.8 muar 50 1000 532 4.9 17.2 0.8 tube shipment (no suffix) c a b muar casablanca
VIPER20/sp/dip - VIPER20a/asp/adip 23/25 1 pentawatt hv tube shipment (no suffix) all dimensions are in mm. base q.ty 50 bulk q.ty 1000 tube length ( 0.5) 532 a 18 b 33.1 c ( 0.1) 1 c b a
24/25 VIPER20/sp/dip - VIPER20a/asp/adip 1 dip-8 tube shipment (no suffix) all dimensions are in mm. base q.ty 20 bulk q.ty 1000 tube length ( 0.5) 532 a 8.4 b 11.2 c ( 0.1) 0.8 a b c
VIPER20/sp/dip - VIPER20a/asp/adip 25/25 1 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy- all rights reserved. stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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